INTRODUCTION TO VHDL
- It is Hardware Description Language .
- It is standard technology independent language.
- Applications are FPGA, CPLD & ASCI programming.
- VHDL is an acronym for VHSlC Hardware Description Language (VHSIC is an acronym for Very High Speed Integrated Circuits).
- The VHDL language can be regarded as an integrated amalgamation of the following languages: sequential language + concurrent language + net-list language + timing specifications + waveform generation language => VHDL Therefore, the language has constructs that enable you to express the concurrent or sequential behavior of a digital system with or without timing.
- Features
• The language can be used as an exchange medium between chip vendors and CAD tool users.
• The language supports hierarchy, that is, a digital system can be modeled as a set of interconnected components; each component, in turn, can be modeled as a set of interconnected subcomponents.
• The language supportsflexible design methodologies: top-down, bottom-up, or mixed.
• The language is not technology-specific, but is capable of supporting technology-specific features.
• It supports both synchronous and asynchronous timing models.
• Various digital modeling techniques such as finite-state machine descriptions, algorithmic descriptions, and boolean equations can be modeled using the language.
• The language is publicly available, human readable, machine readable, and above all, it is not proprietary.
• The language supports three basic different description styles: structural, dataflow, and behavioral. A design may also be expressed in any combination of these three descriptive styles.
• Arbitrarily large designs can be. modeled using the language and there are no limitations that are imposed by the language on the size of the design
• The language has elements that make large scale design modeling easier, for example, components, functions, procedures, and packages.
• There is no need to learn a different language for simulation control. Test benches can be written using the same language to test other VHDL models.
• Nominal propagation delays, min-max delays, setup and hold timing, timing constraints, and spike detection can all be described very naturally in this language.
• The use of generics and attributes in the models facilitate back-annotation of static information such as timing or placement information.
• Generics and attributes are also useful in describing parameterized designs.
• A model can not only describe the functionality of a design, but can also contain information about the design itself 'in terms of user-defined attributes, for example, total area and speed..
• Models written in this language can be verified by simulation since precise simulation semantics are defined for each language construct.
• Behavioral models that conform to a certain synthesis description style are capable of being synthesized to gate-level descriptions.
• The capability of defining new data types provides the power to describe and simulate a new design technique at a very high level of abstraction without any concern about the implementation details.
- To describe an entity, VHDL provides five different types of primary constructs, called" design units. They are
1. Entity declaration
2. Architecture body
3. Configuration declaration
4. Package declaration
5. Package body
Entity Declaration
The entity' declaration specifies the name of the entity being modeled and lists the set of interface ports. Ports are signals through which the entity communicates with the other models in its external environment. Example
entity HALF_ADDER is
port (A, B: in BIT; SUM, CARRY: out BIT);
end HALF_ADDER;
-- This is a comment line
Architecture Body
The internal details of an entity are specified by an architecture body using any of the following modeling styles:
1. As a set of interconnected components (to represent structure),
2. As a set of concurrent assignment statements (to represent dataflow),
3. As a set of sequential assignment statements (to represent be-hav.ior),
4. Any combination of the above three.
Configuration Declaration
A configuration declaration is used to select one of the possibly many architecture bodies that an entity may have, and to bind components, used to represent structure in that architecture body, to entities represented by an entity-architecture pair or by a configuration, that reside in a design library. Consider the following configuration declaration for the HALF_ADDER entity.
library CMOS_LIB, MY_LIB;
configuration HA_BINDING of HALF_ADDER is
for HA-STRUCTURE
for X1:XOR2
use entity CMOS_LIB.XOR_GATE(DATAFLOW);
end for;
for A1:AND2
use configuration MY_LIB.AND_CONFIG;
end for;
end for;
end HA_BINDING;
Package Declaration
A package declaration is used to store a set of common declarations like components, types, procedures, and functions. These declarations can then be imported into other design units using a context clause. Here is an example of a package declaration.
package EXAMPLE_PACK is
type SUMMER is (MAY, JUN, JUL, AUG, SEP);
component D_FLIP_FLOP
port (D, CK: in BIT; Q, QBAR: out BIT);
end component;
constant PIN2PIN_DELAY: TIME := 125 ns;
function INT2BIT_VEC (INT_VALUE: INTEGER)
return BIT_VECTOR;
end EXAMPLE_PACK;
Package Body
A package body is primarily used to store the definitions of functions and procedures that were declared in the corresponding package declaration, and also the complete constant declarations for any deferred constants that appear in the package declaration. Therefore, a package body is always associated with a package declaration;
package body EXAMPLE_PACK is
function INT2BIT_VEC (INT_VALUE: INTEGER)
return BIT_VECTOR is
begin
--Behavior of function described here.
end INT2BIT_VEC;
end EXAMPLE_PACK;
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