Clock Distribution Technique

 

CLOCK DISTRIBUTION TECHNIQUE

 

Clock Distribution:

• In order to control the clock skew the clock distribution technique are used.

• The main problem in clock distribution is the availability of capacitance which plays important role clock to all clocked elements.        
  

•  The clock distribution network or clock tree is the metal and buffer network that distributes the clock to all clocked elements.
  
  
  

 

 Clock Distribution Technique:

 

• There are two complementary ways to improve clock distribution :

1. PHYSICAL DESIGN -                                                                                                                    The layout can be designed to make clock delays more even or at least more predictable.
2. CIRCUIT DESIGN -                                                                                                                        The circuits driving the clock distribution network can be designed to minimize delays using several stages of drivers.

• H-Tree -                                                                                                                                          Regular structure which allows predictable delays.
• Balanced tree - 

                Takes opposite approach of synthesizing a layout based on the characteristics of the circuit to be clocked.

 

 H Tree:

H-Tree

• In this case the widths are adjusted in such way that variations in the load capacitance are as minimum as possible.

• The widths are also adjusted in such a way that the skew throughout the H tree is equal.

• In order to increases the drive capability buffers are also added into the H tree network.

• The H tree network is considered as a top-down technique in which the floor-plan of the H tree finds the floor-plan of the logic.
  

• However, in H tree when memory elements are grouped together, the clock skew increased with physical distance.

 

Advantages: 

• Ideally Zero-skew.

• Can be low power (Depending on skew requirement )

• Low area (Silicon and wiring)

• CAD tool friendly (regular)
  

Disadvantages:

• Sensitive to process variations.
  

• Local clocking loads are inherently non-uniform. 

 

 Balanced Tree:

 

 

 

•  A balanced tree clock network created by using placement and routing in the integrated circuit.

• In this case the clustering is used to guide the placement and a clocking tree is synthesized based on the skew in formation generated during clustering.

• In order to minimize the clock skew the tree balanced.

• Tree is irregular in shape but has been balanced during design to minimize skew.