4Bit DOWN COUNTER

 

4 BIT DOWN COUNTER 

 

 

 

CODE

library IEEE;

use IEEE STD_LOGIC_1164.all;

entity 4bit_counter is

    port(clk, rst, mode:in STD_LOGIC;

            y:out STD_LOGIC_VECTOR (3 downto 0));

end 4bit_counter;

architecture Behavioral of 4bit_counter is

signal temp : STD_LOGIC_VECTOR (3 downto 0));

begin

    process(clk,rst) 

    begin

        if rst='1' then

        temp<="0000";

            elsif clk'event and clk='1' then

                temp<=temp-'1';

        end if;

        end process;

y<=temp;

end Behavioral;