AND Gate

 

 AND Gate

 

 

 

 CODE 

 

library IEEE;

use IEEE STD_LOGIC_1164.all;

entity and_df is

    port(a,b:in STD_LOGIC;

            y:out STD_LOGIC);

end and_df;

architecture data_flow of and_df is

begin

    y<=a and b;

end data_flow;