OR Gate

 OR Gate 

 

 

 

CODE 

 

library IEEE;

use IEEE STD_LOGIC_1164.all;

entity or_df is

    port(a,b:in STD_LOGIC;

            y:out STD_LOGIC);

end or_df;

architecture data_flow of or_df is

begin

    y<=a or b;

                  end data_flow;