Half Adder

 Half Adder

 

CODE

library IEEE;

use IEEE STD_LOGIC_1164.all;

entity half_add_df is

    port(a,b:in STD_LOGIC;

            sum, carry:out STD_LOGIC);

end half_add_df;

architecture data_flow of half_add_df is

begin

    sum<=a xor b;

    carry<=a and b;

                  end data_flow;