Full Adder
CODE
library IEEE;
use IEEE STD_LOGIC_1164.all;
entity full_add_df is
port(a,b,cin:in STD_LOGIC;
sum, carry:out STD_LOGIC);
end full_add_df;
architecture data_flow of full_add_df is
begin
sum<=a xor b xor cin;
carry<=(a and b) or (b and cin) or (a and cin);
end data_flow;
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