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- __4Bit UP COUNTER
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- _UNIT1
- __Syllabus
- __Introduction To VHDL
- __Language Elements
- __Operators
- _UNIT2
- __Clock Skew
- __Jitter
- __Clock Distribution
- __Power Distribution
- __Power Optimization
- __Interconnecting Routing
- _UNIT3
- AI
- _UNIT 1.FOUNDATION
- __Introduction To AI
- _UNIT 2:Searching
- _UNIT 3:Knowledge Representation
- IOT
- _UNIT 1:Fundamentals of IOT
- _UNIT 2:Sensors Networks
- _UNIT 3:Wireless Technologies for IOT
- _UNIT 4:IP Based protocols for IOT
- _UNIT 5:Data Handling & Analytics
- _UNIT 6:Applications of IOT
- CN&S
- _UNIT 1:Introduction to LAN(Local Area Network)
- _UNIT 2:Network Layer Part 1
- _UNIT 3:Network Layer Part 2
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VLSI D&T
Power Distribution
Power Distribution QUE::Explain power distribution and power optimization technique . Power Distribution presents several significant problems, powe…
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VLSI D&T
Power Optimization
Power Optimization QUE::Explain power optimization technique. QUE::Explain power distribution ad power optimization technique. Power optimization…
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VLSI D&T
Interconnecting Routing
Interconnecting Routing QUE::Explain interconnecting routing technique. The basic objective of this design are area , delay, and power floor plann…
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VLSI D&T
Clock Distribution Technique
CLOCK DISTRIBUTION TECHNIQUE Clock Distribution: In order to control the clock skew the clock distribution technique are used. The main problem i…
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VLSI D&T
VLSI D&T
Clock Skew
Clock Skew Que:Explain clock skew and write detail about positive and negative clock skew. ANS : Clock skew means clock riching to flip-flop a…
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VLSI D&T
T Flip_Flop
T Flip-Flop CODE library IEEE; use IEEE STD_LOGIC_1164.all; entity TFF is port(t, clk, rst :in STD_LOGIC; qb:out STD_LOGIC);…
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VLSI D&T
JK Flip_Flop
JK Flip-Flop CODE library IEEE; use IEEE STD_LOGIC_1164.all; entity JKFF is port(j, k, clk, rst :in STD_LOGIC; q, qb:out STD_LO…
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VLSI D&T
SR Flip_Flop
SR Flip-Flop CODE library IEEE; use IEEE STD_LOGIC_1164.all; entity SRFF is port(s, r, clk, rst :in STD_LOGIC; q, qb:out STD_LOG…
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VLSI D&T
D Flip_Flop
D Flip-Flop CODE library IEEE; use IEEE STD_LOGIC_1164.all; entity DFF is port(D, clk, rst :in STD_LOGIC; y:out STD_LOGIC); e…
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VLSI D&T
4Bit DOWN COUNTER
4 BIT DOWN COUNTER CODE library IEEE; use IEEE STD_LOGIC_1164.all; entity 4bit_counter is port(clk, rst, mode:in STD_LOGIC; …
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VLSI D&T
4Bit UP COUNTER
4 BIT UP COUNTER CODE library IEEE; use IEEE STD_LOGIC_1164.all; entity 4bit_counter is port(clk, rst, mode:in STD_LOGIC; …
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VLSI D&T
Full Adder
Full Adder CODE library IEEE; use IEEE STD_LOGIC_1164.all; entity full_add_df is port(a,b,cin:in STD_LOGIC; sum, carry:out STD_L…
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Interconnecting Routing QUE::Explain interconnecting routing technique. The basic objective of this design are area , delay, and power fl... -
Clock Skew Que:Explain clock skew and write detail about positive and negative clock skew. ANS : Clock skew means clock riching to fl... -
JITTER QUE:Explain clock Jitter ? ANS : Clock Jitter is define as the difference between time period of the clock w/f. Due to c... -
Power Distribution QUE::Explain power distribution and power optimization technique . Power Distribution presents several significant probl... -
D Flip-Flop CODE library IEEE; use IEEE STD_LOGIC_1164.all; entity DFF is port(D, clk, rst :in STD_LOGIC; y:out STD_... -
T Flip-Flop CODE library IEEE; use IEEE STD_LOGIC_1164.all; entity TFF is port(t, clk, rst :in STD_LOGIC; qb:out ST... -
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